Digital Systems have evolved to very high densities and have achieved ultra-large-scale integration mainly due to the high degree of design automation available through EDA CAD tools and hardware description languages (HDLs) have been one of the prominent drivers of that automation. Verilog HDL has been one osf the prominent HDLs for the last three decades and due to its closeness with C-language syntactically, it has been the preferred choice of engineers and would be the main HDL employed in this course. However, to take full advantage of the available design automation, proper understanding of the design methodologies, design flows, design partitioning, design abstraction levels, CAD tools capabilities and design blocks is needed.
This course would take advantage of the recent emergence of open-source design flows with rapidly maturing CAD tools complemented by free IC prototyping initiatives such as ChipIgnite from EFabless and Google free shuttle program, which can enable UG students to have their own IC fabricated for free and test it in their labs and therefore trigger a higher level of interest and learning, leading the course students towards future HR of this field.
This course would cover both ASIC and FPGA perspective, which would enable students to understand the trade-offs of both sides. The ASIC design flows would enable the students to touch and explore each and every step of the design flow without being blocked by higher levels of automation targeted towards generic architecture such as in the case of FPGAs. The FPGA perspective would enable the student to have a quick hardware prototype of their design that would lead to actual hardware level interfacing with the instrumentation and observe their design’s performance.
Another purpose of this course is to prepare students to work in a team through project based learning. The tutor would assign selected design tasks through the course projects and would simulate an industry environment where the tutor would be available as a time-limited consultant to guide in the project tasks. This would enable the students to prepare for related industrial experiences.
At the end of this course, students would develop a strong understanding of:
1. Digital design flows and design partitioning.
2. Understand how to design high-density combinational and sequential logics.
3. Get familiar with opensource digital design tools.
4. Go through custom designs of complex data-path structures.
5. Learn finite state machine based design for controller.
5. Learn FPGA based prototyping.
6. Understand backend P&R for both ASIC and FPGA.
7. Learn standard design verification techniques.
This course would enable students to get connected with the recent growing requirement of skilled HR in digital system design locally and globally as well and would make them a feasible candidate for employment of higher studies in this field.
